岗位介绍 1. Develop SRAM/ROM compilers and customized macros.
2. Develop SRAM/ROM characterization flow and deliver design kits.
3. Develop Memory compiler tiling code.
在这个领域发光发热,要具备: 1. Candidate must have a MS degree or above in Electrical or Computer Engineering
2. Knowledge on transistor level circuit design and layout design.
3. Experience in spice simulation or fast spice simulation.
4. Familiarity with Verilog and Synopsys .lib.
5. Ability in scripting language, such as Perl/Python/shell/tcl.
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SPICE Modeling Engineer查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 本科及以上
招聘人数: 若干
职责范围: 1. Testkey design for SPICE modeling
2. SPICE model release for advanced and mainstream process
3. Device characterization
4. Customer support
5. Automation development on all SPICE modeling flow
职位要求: 1. Minimum MS degree majoring in EE, Physics or Engineering related fields.
2. Related experience in semiconductor device, measurement, extraction and SPICE simulation.
3. Proficiency in programming language, such as Perl or Python or C++ or VB.Net.
4. Must be effectively bilingual in Chinese and English.
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Layout Engineer(IP版图设计工程师)查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 本科及以上
招聘人数: 若干
职责范围: 1. Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
2. Work on the physical verification (DRC/LVS/Antenna ...)
3. Work on test chip layout design and verification
4. Close cooperation with designers on PPA optimization
职位要求: 1. At least BS Degree of Microelectronics or Physics.
2. Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
3. Familiar with design rule and layout effect in advanced process.
4. Excellent skills of communication and teamwork are also expected.
5. Programming experience (Perl/tcl skill) will be a plus.
6. Experience in advanced process (n16 and beyond) will be a plus.
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DRC/LVS Development Engineer(DRC/LVS开发工程师)
查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 本科及以上
招聘人数: 若干
职责范围: 1. Work closely with process RD team to develop DRC/LVS for design readiness.
2. Provide customer support to world-wide leading design house.
3. Initial more innovation to continue optimize development efficiency.
4. Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.
5. Work closely with EDA partner for tool qualification and methodology enhance.
职位要求: 1. Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.
2. Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.
3. Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.
4. Ability to work across teams to drive a solution, problem solver and self-motivated.
5. The ideal candidate will have experience in DRC/LVS development.
6. MS or above in EE, CS related fields.
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Digital Circuit Design Engineer(数字电路设计工程师)查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 本科及以上
招聘人数: 若干
职责范围: 1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2. Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
职位要求: 1. Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2. Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred
3. CAD and script capability such as Python/Perl/Shell is preferred.
4. Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5. Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6. Self-motivated and hard work.
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Customer Support查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 本科及以上
招聘人数: 若干
职责范围: 1. This person will be responsible for providing sales related administration and logistics support to customers.
2. Demand forecast
3. Order fulfilment
4. Legal document contract
5. Account data management
6. Credit line control
7. Order handling
8. Production Delivery management
9. Shipment/Logistics arrangement
10. Billing Attainment
11. Finance collection
12. Post service
职位要求: 1. Bachelor degree or above in Business,IE,Management,Trade,Commerce Finance,Economy,related.
2. Initiatively
3. Open and Constructive Communication
4. Teamwork and Cross Team Collaboration
5. Customer Orientation
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职责范围: 1. Rotate within Accounting: Accounting Operations,Accounting Services and Financial Planning & Analysis.
职位要求: 1. Bachelor degree or above with major in Accounting,Finance or Economics
2. Working experience in well-known international Accounting Firms is a plus
3. Logical thinking and self-motivated
4. Good communication skills
5. Team player and quick learner
6. Skilled at MS Office
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职责范围: 1. To be responsible for helping to drive leading edge process/device development/manufacture ability requirements, yield enhancement and defect reduction on advanced technology.
2. Identify and solve tool/process induce defect problems.
职位要求: 1. Minimum master degree in Electric Engineering, Physics, Materials science or other related background.
2. Exhibit good and open communication skills, be able to work within cross-functional teams.
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良率精进工程师2022届查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
职责范围:
1. To be responsible for helping to drive leading edge process/device development/manufacture ability requirements, yield enhancement and defect reduction on advanced technology.
2. Identify and solve tool/process induce defect problems.
职位要求: 1. Minimum master degree in Electric Engineering, Physics, Materials science or other related background.
2. Exhibit good and open communication skills, be able to work within cross-functional teams.
实习时间: 7/12~8/27.周工作时间4天及以上(不含周六日)
实习地点: 江苏省南京市浦口经济开发区紫峰路16号
表现优秀的暑期实习生更有机会提前获得台积电南京公司的正式offer哦!
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Job content: 1. Automatic Material Handling System (AMHS) Engineer, Normal Shift
2. A highly motivated individual with a strong technical background and capability to planning and sustain AMHS devices such as OHT, Stocker, Sorter, N2 Charger and auto-pack /unpack.
3. Working with a team which may include MFG, Module, Quality team to achieve productivity, efficiency, quality excellence.
4. Cross-fab team work with other site's AMHS memeber to complete top-down tasks.
5. Lead and drive external supplier in Taiwan, Japan, Europe, America area to develop new devices and delivery on time.
6. Analysis and optimize AMHS transportation bottleneck.
7. Inovate for problem solving and tool performance improvement.
8. Be responsible for sustaining ownership such as day-to-day operations, equipment troubleshooting and mentoring technicians.
工作内容: 1.自动化物料搬运系统(AMHS),常日班
2.具有强烈的上进心,专业的技术背景,并具备很强的能力可以规划和维护AMHS设备,例如OHT,Stocker,Sorter,N2 Charger和自动包装/拆包机。
3.与包括制造部,工程部和质量团队在内的团队合作,以实现产能,效率和卓越品质。
4.与其他厂区的AMHS成员进行跨工厂的团队合作,一起完成被交付的任务。
5.主导并推动台湾,日本,欧洲和美洲地区的外部供应商开发新设备并准时交付。
6.分析和优化AMHS搬运瓶颈。
7.用创新的方法解决问题和改善机台性能。
8.负责日常维护,设备故障排除和指导一线技术人员。
Requirement: 1. Bachelor or Master degrees in an engineering field such as Mechanical Engineering, Electrical Engineering, Engineering Management, Transportation Management, Information Engineering.
2. Exhibit good and open communication skills, be able to work within cross-functional teams, including internal and external partners.
3. Hands-on participation and a strong sense of ownership.
4. Fluent in English.
5. No experience allowed, with data analysis, SQL skill, algorithm knowledge prefer.
要求: 1.机械工程,电气工程,工程管理,运输管理,信息工程等工程领域,学士或硕士及以上学位。
2.具有良好和开放的沟通能力,能够在包括内部和外部合作伙伴在内的跨职能团队中工作。
3.动手能力强和具有强烈的责任感。
4.英语流利。
5.无需工作经验,具有数据分析,SQL技能,算法知识者优先。
立即申请
职责范围: 1. Support Fab to maintain and deploy Intelligent Manufacturing Technology and Automation Systems.
2. Communicate with users to define requirements, design, implement, and deploy systems, and continuously improve them using software engineering methodology.
3. Quality Defense system management, KPI tracing and analysis, supporting users to improve manufacturing quality andefficiency.
职位要求: 1. Master degree or above and major in Industrial Engineering, Computer Science or Computer Engineering related fields.
2. Strong technical skills in at least one of the following fields: Database, JAVA, .NET., C#, Python, Optimization algorithm application, Statistics and math tools(MATLAB, R), and coding
3. Familiar with fab manufacturing operation is a plus.
4. Good communication skill, highly stress resistance.
5. Willing to take challenges and co-work with others .
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Digital circuit design engineer(数字电路设计工程师)查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士及以上
招聘人数: 若干
职责范围: 1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2. Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
职位要求: 1. Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2. Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred
3. CAD and script capability such as Python/Perl/Shell is preferred.
4. Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5. Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6. Self-motivated and hard work.
立即申请
IC Frontend design engineer(芯片前端设计工程师)查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士及以上
招聘人数: 若干
职责范围: 1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2. Design flow/methodology development and innovation for front-end design challenges.
3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
职位要求: 1. MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2. New graduate or 3+ years working experience.
3. Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4. Familiar with tcl/Perl/Python program.
职责范围: 1. Physical implementation of advanced technology chips.
2. Design methodology development and innovation for advanced technology challenges.
3. Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.
4. Be responsible for advanced node PPA benchmark, and solution development.
5. EDA tool new features enablement.
6. Customer onsite/offsite supports will be required on demand.
职位要求: 1. MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.
2. New graduate or 3+ years working experience in chip physical implementation.
3. Familiar with Synopsys/Cadence APR tools/flows.
4. Familiar with TCL/Perl/Python programming.
5. Experience with TSMC advanced technology is plus.
6. Proven record in production tape-outs is plus.
职责范围: 1. Develop SRAM/ROM compilers and customized macros.
2. Develop SRAM/ROM characterization flow and deliver design kits.
3. Develop Memory compiler tiling code.
职位要求: 1. Candidate must have a MS degree or above in Electrical or Computer Engineering
2. Knowledge on transistor level circuit design and layout design.
3. Experience in spice simulation or fast spice simulation.
4. Familiarity with Verilog and Synopsys .lib.
5. Ability in scripting language, such as Perl/Python/shell/tcl.
立即申请
IC CAD and Methodology engineer(芯片计算机辅助设计暨设计方法论工程师)查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士及以上
招聘人数: 若干
职责范围: 1. Develop chip implementation infrastructure, include but not limited to general design flow automation, design collateral/environment/data management, computing resource allocation/analysis/monitoring, and design
diagnosis solutions development.
2. Develop chip implementation methodology algorithms to improve productivity and design PPA by machine learning and/or expert system programming.
3. Develop chip implementation environment regression automation and code review system to improve source code quality and readability.
职位要求: 1. MS degree or above in EE, CS related fields.
2. Proactive, self-motivated, and willing to take challenges
3. Familiar with Python3 or C/C++ programming languages
4. Familiar with Linux environment and operations
职责范围: 1.Responsible for checking the advanced chip function before fabrication. Given the verification, the chip can exhibit expecting high performance after fabrication.
2.Reliable flow setting, identify violation root cause, and provide the fixing strategy to achieve high quality chips.
3.Professional at one domain of blow knowledge at least. Signoff team not only executes the advanced signoff skill, but also push the boundary of flow to reach higher quality and productivity.
a.STA (static timing analysis): using commercial timing signoff EDA tool combining advanced on-chip timing analysis method (OCV) to achieve timing closure before tape-out.
b.IR analysis: define the reasonable IR drop spec, and explore the opportunity to realize the function with sufficient voltage support and reasonable power consumption.
c.PV (physical verification): verify and achieve the chip without DRC (design rule check) and LVS (layout versus schematic). With the verification, the following fabrication can minimize the defect and reach high yield
performance.
职位要求: 1.MS degree or above in EE, CS, Physics or related domains. Experience in Digital IC design flow, especially signoff, is a plus
2.Innovative, persistence and flexible personality.
3.For frequent cross team cooperation and customer support, excellent communication/presentation skill
Recommended requirements (plus): 1.Excellent English skill, CET6
2.Software skill, ex: tcl, python
职责范围: 1.Work closely with process RD team to develop DRC/LVS for design readiness.
2.Provide customer support to world-wide leading design house.
3.Initial more innovation to continue optimize development efficiency.
4.Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.
5.Work closely with EDA partner for tool qualification and methodology enhance.
职位要求: 1.Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.
2.Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.
3.Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.
4.Ability to work across teams to drive a solution, problem solver and self-motivated.
5.The ideal candidate will have experience in DRC/LVS development.
6.MS or above in EE, CS related fields.
立即申请
Layout Engineer(IP版图设计工程师)查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 本科及以上
招聘人数: 若干
Role and Responsibility 1.Full layout design for std cell/IO/SRAM IPs in advanced node
2.Work on the physical verification(DRC/LVS/Antenna ...)
3.Work on test chip layout design and verification
4.Close cooperation with designers on PPA optimization
Requirement 1.At least BS Degree of Microelectronics or Physics.
2.Excellent graduate or at least 1 years' related working experience
3.Familiar with layout design and verification tools(Virtuoso,Laker,Calibre)
4.Familiar with design rule and layout effect in advanced process.
5.Excellent skills of communication and teamwork are also expected.
6.Programming experience(perl/tcl skill) will be a plus.
7.Experience in advanced process (n16 and beyond) will be a plus.
立即申请
IC设计工程师所属的设计暨技术平台设立于1999年,主要作为台积公司与IC设计客户之间的沟通桥梁。除了专业技术之外,IC设计工程师也负责执行与客户或内部的许多项目。
Who we work with
IC设计公司/ 内部研发单位/ EDA供货商
Who we look for
设计暨技术平台欢迎任何兼具有创意及实做肯做的工作态度的人,加入这个特别组织。IC设计工程师不仅注重工作质量,更重要的是如何快乐、有效率地工作。
任何具有微电子、电子科学与技术、集成电路设计等相关专业硕士背景的应征者,都欢迎投递履历应征IC设计工程师的工作。
实习时间: 7/12~8/27,周工作时间4天及以上(不含周六日)
实习地点:江宁九龙湖国际企业总部园
表现优秀的暑期实习生更有机会提前获得台积电南京公司的正式offer哦!
立即申请